FACCU: Enable Fast Accumulation for High-Speed DSP Systems

A number of fast accumulation (FACCU) designs are proposed for one of the essential components in DSP systems, the accumulator, to largely boost the DSP’s maximum attainable processing speed. By leveraging the unique features of the accumulator, the loop-incorporated critical path is reduced to as short as one or two full adders without degrading the sampling rate, thus efficiently addressing the system bottleneck caused by the recursive loop in accumulation. Based on this innovation, several highly scalable FACCU architectures are developed to meet various high-speed requirements with minimal overhead. Moreover, novel system-level co-optimization skills are developed in FACCU variants for two commonly used subsystems involving accumulators (the AdderTree-SA and the Distributed Arithmetic architecture) to achieve the best trade-off between area and speed, which have not been well investigated in previous works. Implementation results under the SMIC 55nm technology demonstrate that the proposed FACCU designs have great superiority in critical path delay, area, and latency compared with both prior art and the accumulators deeply optimized with the EDA tool. The application-level evaluations are also conducted for an FACCU-incorporated hardware accelerator of image processing network, demonstrating that the developed FACCU can efficiently improve the throughput in a real system.