Performance Analysis of 4-Bit Multiplier using 90nm Technology

This paper explores three different 4-bit multipliers built using a modified full adder at the 90nm technology and compares low-power, high-speed multiplier designs with their CMOS counterparts. Since the multiplier block consumes a lot of power and plays a big part in the circuit's speed, the proposed multiplier will help in optimizing and enhancing the circuit performance. Our analysis results suggest that the proposed multipliers offer a decrease in power up to ~47.6%, a decrease in delay up to ~63.96%, and a decrease in transistor count up to ~58.7% when compared with the CMOS based designs.