An Efficient Design of GNRFET based Quaternary Logic Gates

This paper presents an efficient design of Multi-Valued Logic (MVL) based armchair Graphene Nano Ribbon Field Effect Transistor (GNRFET) gates and their performance analysis. In this work, voltage mode architecture with voltage division structure is used to implement quaternary logic. The basic gates are implemented to confirm the functionality of this architecture using voltage divider. Quaternary NAND (QNAND) and Quaternary NOR (QNOR) gates are considered to enhance the performance parameters such as delay and power delay product (PDP). The designs are simulated using Synopsis HSPICE simulation tool, using the 32-nm MOS-GNRFETs technology node and 0.9V as supply voltage. It is observed that the new designs are showing optimized delay and PDP parameters as compared to Carbon Nano Tube Field Effect Transistor (CNTFET) based existing designs. Compare with the previous works, the proposed QNAND gate has been optimized by 11.3 % and 58.47 % of delay and PDP, respectively. Similarly, QNOR gate has been optimized by 12.59 % and 68.25 % of delay and PDP, respectively.