A 28-nm 198.9-TOPS/W Fault-Tolerant Stochastic Computing Neural Network Processor

Previous energy-efficient neural network (NN) processors suffer from bit errors when operating at lower voltages for further power reduction. Stochastic computing (SC) shows great potential due to its low hardware cost and high fault tolerance. Conventionally, limited by the long latency of bitstreams, SC-based NN accelerators adopt a hybrid stochastic-binary architecture, sacrificing fault tolerance and hardware efficiency. This letter proposes a fully SC architecture that maximizes fault tolerance while offering excellent energy and area efficiency. The fabricated 28-nm prototype is the
first
silicon-proven SC-based NN processor, realizing an energy efficiency of 198.9 TOPS/W and an area efficiency of 2630 GOPS/mm
²
with an accuracy loss reduction of 70%.