Investigation on SiC MOSFET’s Avalanche and Short-Circuit Failure Mechanism

Avalanche and short-circuit failure are both common reliability problems for SiC MOSFET in industrial applications. Methods in prior research based on experiments are difficult to clarify mechanisms of SiC MOSFET’s avalanche and short-circuit failure. By using TCAD simulation software, a cell-level simulation model is established and failure mechanisms are investigated from a micro perspective. Combining external characteristics and internal parameters distribution inside the cell during failure happens, we clarify the physical mechanisms of both failures. Results show that the common reason for SiC MOSFET’s avalanche and short-circuit failure is that high temperature increases bipolar leakage current of parasitic BJT, forming positive feedback increasing channel current and temperature, which make the parasitic BJT unable to turn off. In avalanche failure mode, BJT’s current amplification effect accelerate increase of parasitic BJT’s current. Finally, we analyze impacts of SiC MOSFET’s cell-design parameters on short-circuit tolerance, which are proved by simulations.