Power, Performance, and Area Analysis of Hardware Design Techniques for GF(2k) Greatest Common Divisor computation

Computation of the greatest common divisor (GCD) for two non-zero polynomials plays a vital role in several applications including cryptography, error-correcting codes, linear systems, and control systems. Several of these applications that involve finite-field arithmetic, use classical algorithm such as Euclid’s algorithm for the computation of GCD. This paper presents a new algorithm called successive polynomial XOR (SPX) to compute the GCD. Two implementation techniques: (1) pure combinational logic, and (2) finite state machine with data-path (FSMD), are used to implement the classical Euclid’s algorithm and the SPX algorithm. Both Euclid and SPX are implemented using 28 nm CMOS process; and a detailed power/ area/ performance analysis is performed using Synopsys design tools. Results show that the combinational implementation of the SPX algorithm utilizes significantly lesser area than the Euclid’s algorithm. For example, for degree six polynomial, the combinational SPX consumes approximately $255. 43 \mu m^{2}$ less area as compared to the combinational Euclid. The FSMD implementation of the SPX algorithm reduces both dynamic and leakage power consumption. The proposed SPX algorithm is also found to be significantly faster in computing the GCD than the Euclid’s algorithm by a factor of 4.7 and 2.1 for combinational and FSMD logic respectively.