An ASIC Architecture With Inter-Chip Networking for Individual Control of Adaptive-Metamaterial Cells

In this paper, the architecture of an application-specific integrated circuit for adaptive metasurfaces is presented. The architecture allows scalable networking over large metasurfaces and reconfiguration of each unit-cell with unique complex impedance settings, for adjusting metasurface electromagnetic performance. The one-chip-design metasurface array, includes self-initialization/addressing, configuration-packet routing, and network adaptation for fault-tolerant dynamic metasurfaces. An asynchronous design is adopted for power efficiency and high scalability, whereas speed is enhanced through multilevel pipelining. The ability to dynamically form reconfigurable networks in conjunction with the clockless operation helps the metasurface to cover arbitrary physical shapes, implemented on both rigid or flexible substrates. The architecture is validated through transistor-level simulations of the complete design implemented in a commercially available process. Then, a variety of scalable and/or flexible networks are presented, exploiting the strengths offered by the architecture, to demonstrate its capabilities and estimated performance. The demonstrated results of the architecture and its networking capabilities, allow the realization of chip-to-chip programmability of metasurfaces with up to 2
¹⁸
ASICs. The individual ASICs can be reconfigured in
$2 ~\mu \text{s}$
and consume only
$342 ~\mu \text{W}$
of static power.