Automatic Timing ECO Using Stage-based Path Delay Prediction

Due to the increasing IC design complexity, Engineering Change Orders (ECOs) have become a necessary technique to resolve late-found functional and/or timing violations. ECO is a step that requires a lot of engineer experience and manual operation, and requires multiple static timing analyses (STA) loop iterations. Due to the complexity of static timing analyses after timing ECO, it is difficult to predict whether the timing converges after performing timing ECO. In this paper we propose an ECO algorithm that utilizes the "gate + wire" delay prediction as a guide. Unlike conventional ECO algorithm, we extract data from cell information and previous timing reports to train machine learning models for fast timing predictions, to guide the generation of efficient ECOS. Our way considered the time of STA and reduce the number of iterations required. We use the machine learning model for rapid timing prediction, and then quickly generate ECO to fix timing violations. Experimental results demonstrate that the average absolute error between predicted path delay and real path delay is 2.61ps, the average relative percentage error is only 0.35%, and the average absolute error of "gate + wire" delay is only 1.03ps.