High precision calibration method for asynchronous time-to-digital converters

Field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) suffer from large bin width variations. This issue imposes performing a calibration process to compensate the nonlinearity of the TDC. The most commonly used calibration technique is the bin–by-bin calibration that can improve the differential nonlinearity (DNL) of the TDC up to 10 times. In this paper, we propose a new robust calibration method for asynchronous TDCs and compare it with the bin-by-bin method. The simulation results showed that the proposed method is less sensitive to the nonlinearity of the TDC, and an improvement of more than 100 times can be achieved in regard to the DNL of the non-calibrated TDC. These results have been confirmed by experimental measurements made on an asynchronous TDC implemented on a Cyclone V SoC-FPGA kit. Density code tests were performed to measure the root mean square (RMS) DNL of the TDC and those of the calibrated histograms for the two methods. For a TDC with a DNL of 0.71 least significant bit (LSB), the DNL of the calibrated histogram is 0.053 LSB for the classical bin-by-bin method and 0.005 LSB, i.e., 10 times better, for the proposed method.