Design and Analysis of FinFET based 10T SRAM Cell for Low Power Applications

Portable gadgets such as mobile phones and laptops are in high demand, and they require increased performance as well as lower power dissipation. Low power memory circuits are frequently used in these gadgets to maintain the backup batteries. In this regard, a new 10T static random access memory (SRAM) cell with increased stability, medium throughput, and lower power consumption has been built and evaluated. The Cadence virtuoso tool was used to evaluate the 18nm technology node’s predicted topology. The read decoupling approach is employed in the proposed 10T cell to improve read stability, while leakage power is reduced by stacking transistors in the core latch. The read/write power dissipation in a 10T Memory cell is 63.6 percent / 39.9 percent lower than in a normal 6T Memory cell. In comparison to a conventional 6T SRAM cell, read/write reliability is enhanced by 1.91/1.53 times. Furthermore, when compared to a normal 6T SRAM cell, read access latency is reduced by 1.2 times. However, the suggested 10T SRAM cell’s write latency is 1.6 times that of a typical 6T Memory cell.