A Time-Interleaved Extended-Counting Incremental $\Delta \Sigma$ for Low-Noise High-Speed 3D-Stacked CMOS Image Sensors

This letter introduces a time-interleaved pipelined extended-counting incremental
$\Delta \Sigma$
(
$\text{I} \Delta \Sigma$
) analog-to-digital converter (ADC) in order to achieve high readout speeds for 3D-stacked CMOS image sensors while still maintaining continuous rolling shutter. By using first-order
$\text{I} \Delta \Sigma$
ADCs as substages and resharing hardware between substages, an area-efficient implementation is possible. This ADC architecture achieves a high sampling rate of 2.97 MS/s and an effective number of bits of 12 bits and consumes 680
$\mu$
W. This results in a record figure of merit of 58 fJ/conv.step in a 45-nm CMOS technology.