Designing an Arithmetic Logic Unit (ALU) in virtual laboratory in 3D

In teaching electronic, telecommunications and related engineering, the Arithmetic-Logic Unit (ALU) is a basic device for understanding digital electronics and binary and combinational logic. This research is developed in collaboration with UNAD (Colombia) and UNED (Costa Rica) for the design and implementation of an ALU adding two words of two bits in a virtual laboratory. The design is carried out using Karnaugth mapping techniques, geometric modeling in SketchUp, programming with blueprints and the Unreal Engine graphics engine for its incorporation in the virtual laboratory.