Learning-Based On-Chip Parallel Interconnect Delay Estimation

Interconnect is a crucial challenge to achieve overall chip performance in current and future technology nodes. An accurate, universal, and portable delay model is essential for interconnects’ analysis and coding development. Machine learning algorithms are used in many applications and provide solutions for problems that are difficult to achieve using conventional approaches. Using machine learning techniques for delay estimation can be helpful since they can capture the complex behavior of the propagation of the signals. This paper proposes a neural-network learning-based delay model for parallel multi-segment interconnects using a conventional multi-layer perceptron network. For the network to learn the complex signals’ misalignment effect, we propose a framework to transform initial delay data into a learnable set of numbers. This transformation process is critical to have an accurate delay estimation. The proposed model has been validated using commercial 65 nm technology. The results show significant improvement in accuracy compared with previous models.