Novel Distributed Placement Techniques Based on Routing Network for TMR Designs

Triple modular redundancy (TMR) is the most widely used FPGA circuit hardening technology to mitigate soft error. Generating the TMR circuits based on high level synthesis technology (HLS) has become a new research branch due to its good timing performance. However, the TMR circuits implemented in FPGA will be affected by common mode failure (CMF), which leads to the decline of fault tolerance. The commonly used distributed placement techniques to mitigate CMF will have a negative impact on the timing performance. In this paper, a novel distributed placement technique based on routing network is proposed. The spacing of redundant branches is divided by the distance characteristics of routing resources. Some distributed placement strategies are designed to explore the influence of distributed placement strategy on timing and fault tolerance. The experimental results show that the method proposed can be used to determine the optimal distributed placement strategy to achieve the best trade-off between timing and fault tolerance.