Improving Simulated Annealing Algorithm for FPGA Placement Based on Reinforcement Learning

As the increasing complexity and capacity of large-scale integrated circuit devices, Field Programmable Gate Array (FPGA) has been widely concerned and applied with its high degree of concurrency., customizable and reconfigurable features. Thereby., the importance of efficient Electronic Design Automation (EDA) tools for modern FPGA is hard to overestimate. As a key link in the FPGA EDA design flow, the significance of placement technology for FPGA is self-evident. Simulated annealing is widely used in FPGA placement as an independent algorithm or an enhancement step of analytical placement algorithms. However, as the inherent properties of circuit cannot be utilized by the traditional simulated annealing algorithm, it depends on tremendous random swap operations, which is very time-consuming, making it cannot keep up with the increasing design scale and FPGA chip resources. In this paper, we propose an improving simulated annealing placer based on reinforcement learning. Many types of search region construction methods are proposed in which the placer can explore the solution space more efficiently, and thus can avoid exploring the redundant design space. Then, an intelligent strategy for selecting the most powerful search regions based on reinforcement learning is investigated to further ameliorate the applicability of the placer. Experimental results show that the proposed scheme can reduce the runtime while maintaining the wirelength and critical path delays compared with the simulated annealing algorithm.