Research on Bitstream Configuration Technology of Programmable SoC Mass Production Test Based on Reconfiguration Mechanism

With the advancement of integrated circuit technology and the pressing need for Hardware-Software Codesign in real-world scenarios, FPGA producers started to set in processor cores in the chip design, resulting in the emergence of a new circuit architecture with both software and hardware programmable features, dubbed programmable SoC. In comparison to standard FPGA, the architecture and functioning characteristics of programmable SoC have evolved dramatically. As a result, in the mass production testing, the same bitstream configuration approach based on the SelectMAP interface as regular FPGA is unable to achieve. This study presents a mass production test bitstream configuration method based on a reconfiguration mechanism for the Xilinx Zynq-7000 series programmable SoC. This technology is mainly made up of three sections: program solidification and test bitstream storage based on SD card, bitstream reconfiguration based on PCAP path, and configuration bitstream switching based on GPIO interrupt. Finally, the proposed technology is verified by experiments, and experiments are designed to compare the test configuration time based on JTAG path and PCAP path. In contrast, this technology has the characteristics of high configuration efficiency and can be fully applied to the mass production test of this series of Programmable SoC circuits.