An Energy Efficient Static Address Decoder for High-Speed Memory Applications

The Static address decoder plays a vital role in the design of memory architecture. It lies in the critical path that affects the execution of the memory speed due to the internal complexity of the circuit. This paper proposes a 2 to 4 static address decoder circuit, which requires 12 Transistors using Hybrid CMOS Logic. When compared to the existing Mixed-Line logic decoder, the proposed one occupies less number of transistors; the power dissipation of about 15% and 3% of the area is minimized. The simulation results of the decoder are carried out at VDD = 0.8 V using the Mentor Graphics EldoSpice at 22 nm CMOS technology. The simulation results are extended to 4-to-16 and 5-to-32 decoders; utilize 8% and 15% less amount of propagation delay compared to existing 4-to-16 and 5-to-32 Modified Mixed Logic decoders. The performance of the proposed 2-to-4 decoder circuit compared with the 2 to 4 Mixed (PT-TG) Logic, pseudo-NOR Logic and Standard CMOS Logic shows 30%, 45%, and 58% reduction of Power-Delay Product (PDP). By using Euler’s path approach, the proposed 2 to 4 decoder circuit occupies an area of about $4. 01 \mu m^{2}$ on a silicon chip, reduced by 3% of area compare to mixed-logic line decoder. The layout of the circuit is drawn using the Mentor Graphics Calibre tool.