A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter

This paper presents an inductorless cascaded phase-locked loop (PLL) with ultralow jitter that leverages the large performance gap between low- and high-frequency ring oscillators. A single-stage sample-and-hold (S/H) subsampling phase detector (SSPD) is proposed for the 1
^st
stage, where the oscillator’s control voltage is updated only when the impulse sensitivity function (ISF) is zero, enabling wider loop bandwidth (BW), lower jitter, and lower spur. Fabricated in 65-nm CMOS, the prototype operating at 10GHz achieves −63-dBc reference spur, 175-fs integrated RMS jitter and −240-dB FOMjitter with a 125-MHz reference clock.