Demonstration of High Endurance Capability on Mega-Bit RRAM Macro and Model of ppm Level Failures

In this work, mega bit level high endurance capability on RRAM array embedded in standard 28nm platform is firstly demonstrated. 500K and 1M cycles endurance is achievable with 2 bits and 3 bits error correction code design scheme, respectively, by well optimized SET and RESET strength in programming algorithm. In addition, within array configuration of conductive filament in statistical view is analyzed by current model fitting. At 0 state, higher resistance bit and post cycling array exemplified partially ruptured filament. Moreover, inspired by polarity independent failure behavior, additional forming path initiated by field induced dielectric breakdown is suggested as the root cause of ppm level failures during endurance. The proposed model is validated by trap assist tunneling based Monte-Carlo simulation and is in good agreement with experimental phenomenon.