A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency

Herein, the development of a 2-Layer Transistor Pixel stacked CMOS image sensor (CIS) that possesses a large full well capacity (FWC) and high quantum efficiency (QE) is demonstrated. Photodiodes (PDs) and pixel transistors are fabricated on different Si layers by a three-dimensional sequential integration process to increase the PD volumes, and new sublocal connections that connect multiple floating diffusions are introduced to improve the conversion gain and random noise. Silicon oxide is used as the embedded material for full trench isolations (FTIs) for the first time instead of conventional poly-Si to prevent light from being absorbed by the FTIs, and the QE at a wavelength of 530 nm increases by 19%. We have demonstrated a 1.0 μm dual PD CIS with an FWC of 12,000 e-, much larger than the previous CISs with larger pixel sizes.