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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET | IEEE Conference Publication | IEEE Xplore
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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET

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Aida Varzaghani; Bardia Bozorgzadeh; Jack Lam; Ankush Goel; Xiaobin Yuan; Mohamed Elzeftawi
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Abstract:

A low-power transceiver using a flexible clocking scheme is presented to enable the entire range of rates for Ethernet and PCIe applications. In addition, each lane can i...Show More

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Abstract:

A low-power transceiver using a flexible clocking scheme is presented to enable the entire range of rates for Ethernet and PCIe applications. In addition, each lane can independently support any data rate within the same protocol. Implemented in 5nm FinFET, the quad transceiver occupies 1806×825μm2 and achieves a total power efficiency of 5.6pJ/b per lane including analog and DSP at 112Gb/s.
Published in: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Date of Conference: 12-17 June 2022
Date Added to IEEE Xplore: 22 July 2022
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ISSN Information:

DOI: 10.1109/VLSITechnologyandCir46769.2022.9830304
Conference Location: Honolulu, HI, USA
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