A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier

This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in a residue amplifier of a pipelined SAR ADC. It uses an open-loop dynamic amplifier that exploits a capacitive degeneration, and its limited voltage gain is improved to 16× by using a two-stage configuration. Since the optimal timing of the voltage gain to achieve high linearity can be set with a simple timing generator, the error due to incomplete settling of the residue amplifier can be maintained with negligible power overhead. Fabricated in a 65-nm CMOS process, the pipelined SAR ADC achieves 65-dB SNDR and 79.8-dB SFDR at a sampling rate of 50 MS/s, while consuming only 0.46 mW. This corresponds to a Walden FoM of 6.33 fJ/conv.-step and a Schreier FoM of 172.35 dB.