Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS

In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.