A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoM
Walden
of 305fJ/c-s.