A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V

A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm
²
is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm
²
) and Cell efficiency (68.1%).