Performance Analysis of Silicon Nanowire FET for GAA and Pi Gate Configurations

Short channel effects can affect the performance of a transistor wildly depending on the specifics of the component. This paper investigates and studies the performance of specific silicon nanowire field-effect transistors (SiNW FETs) along varying channel length, temperature, and oxide thickness for two different gate configurations: Gate All Around and Pi gate. The performance will be gauged by the I-V characteristics, mid-channel conduction band profile, and mid-channel charge density profile. The simulation has been carried out by a tool named ‘Multi-gate Nanowire FET’. A Nanowire FET’s drain current decreases by increasing the length of the channel and the thickness of oxide, whereas it rises by increasing the temperature. GAA is also seen to have better device control because of its lower leakage current than any other gate and a higher conduction band energy that is 77.94% (at 15 nm) than the Pi gate.