An Optimal Block-Scheduling Algorithm for Pipelined Block-Parallel LDPC Decoder

Since the low-density parity-check (LDPC) code is widely used in today's wireless communication standards, its decoder architecture has been discussed in many works. To achieve high universality in hardware implementation, block-parallel is applied in the decoder for quasi-cyclic (QC) LDPC code. Configurability can be easily achieved by designing the operation instructions for blocks. The pipeline is also introduced as a traditional scheme for higher throughput. However, because of the data dependence in the decoding process, the pipeline would cause read-write conflicts, and some techniques should be utilized to solve them. Thanks to the block-parallel architecture, re-scheduling of the blocks can reduce the conflicts, but cannot guarantee the total avoidance of them. Inserting no-operation instructions (NOPs) is another solution that can remove all potential conflicts at the cost of lower throughput. In this paper, we combine these two techniques and propose an optimal algorithm for the instruction design aiming at the pipelined block-parallel decoder. It is proved that our algorithm can generate decoding instructions with no read-write conflict by inserting the minimum number of NOPs.