A New Reduced Switch Seven-Level Triple Boost Switched Capacitor Based Inverter

This paper proposes a new reduced switch count seven-level triple boost inverter based on switched capacitor technique. The proposed topology has fewer number of components and has the ability of balancing the voltage across the capacitors. The structure of the proposed topology is very simple and can be easily extended to higher number of voltage levels. The generalized structure for higher number of levels is presented. The level shifted pulse width modulation approach is used to evaluate the proposed topology. In addition, design of switched capacitors and power loss calculation of semiconductor switches are provided. This proposed inverter topology is compared with the state-of-art topologies to demonstrate its superior performance. Further, thermal modelling of the topology is done in PLECS to calculate the power losses and efficiency. Finally, this proposed 7-level topology is simulated using MATLAB/Simulink and tested on experimental prototype for the performance verification and the results are included.