Area-Efficient Partially-Pipelined Architecture for Fast-SSC Decoding of Polar Codes

We propose a method to reduce the area of the state-of-the-art fully-unrolled partially-pipelined architecture for Fast Simplified Successive-Cancellation (Fast-SSC) decoding of polar codes. In state-of-the-art partially-pipelined architecture, compute units are idle during many of the clock cycles. The proposed solution alleviates some of this inefficiency. As a result, without degrading throughput or latency, area is reduced. For instance, compared to non-pipelined method, the proposed area-efficient partially-pipelined architecture reduces the area by a factor of $9.5\times$ at initiation interval $I=20$, while the state-of-the-art partially-pipelined architecture reduces the area by a factor of $7.4\times$. Hence, area efficiency is increased by a factor of about $1.28\times$ in this case.