In 12nm FinFET Technology, performance analysis of low power 6T SRAM layout designs with two different topologies

Using 12nm FinFET technology, a model for a 6T SRAM cell was constructed. Cadence Virtuoso software is used to produce two bespoke layout bit cell designs. In terms of stability, read and write performance, power consumption and layout space, these two layout concepts are compared. To determine the stability of the SRAM cell Static Noise Margin (SNM) analysis is used. The unit layout plans are presented and the 16bit arrays are built utilizing these designs. The unit cell as well as the array of Layout Type 1 has the least power dissipation of around 12% and comparatively less delay than that of Layout Type 2. But the Layout Type 2 has a bit-cell area decrease of around 10%. Cadence Tool was used to design the 6T SRAM cell and all the simulations were performed using 12nm CMOS technology, Hspice, Spectre and 0.8 volts as the supply voltage.