27/38 GHz Dual-Band Subsampling PLL Design with Automated Frequency Calibration

This paper presents a 27/38 GHz dual-band frequency synthesizer with a 2-stage cascaded structure. The 1st stage is a 5.5 GHz integer-N charge pump PLL and the 2nd stage is a reconfigurable sub-sampling PLL for dual band frequency synthesis. By utilizing the sub-sampling PLL, it eliminates the frequency divider which leverages phase noise performance. An automated frequency calibration (AFC) loop is designed that can select a proper control word to set VCO’s initial frequency. In addition, the frequency band switching is controlled by changing the target division ratio in the AFC loop. The circuit is designed using the Global Foundries 45 nm CMOS SOI technology. The simulation results validate that the circuit can rapidly lock at 27.5 GHz and 38.5 GHz with the phase noise being −115 dBc/Hz at 10 MHz offset.