A fast low power embedded cache memory design

A 64 kb cache system designed for 32 bit RISC CPU is realized. The circuits include two 4 ns 32 kb cache memories, two 1.4 ns 64-entry direct mapped translation lookaside buffers (TLB), and two 2 ns 64-lines tagRAM. The high-speed decoder and amplifier are employed. The TLB design contains a line encoder and valid bits with flash clear. This cache memory reduces the power and has faster access time by using the optimized decoder and sense amplifier. SMARCH algorithm makes all the cache system self-testability.