Design of a low latency high speed pipelining multiplier

A low latency pipelined multiplier architecture using Booth encoding technique is presented in this paper. Based on such architecture, a 16-bit multiplier, with only 5 cycles latency and about 5,000 equivalent logic gates, had been designed and integrated into the DSP core that is a key component of the four-channel CODEC chip. The chip was fabricated in 0.5 um double-poly three-metal CMOS technology. Testing results show that the multiplier can work at a more than 100 MHz clock frequency.