CMOS-Integrated High-Voltage Transformer for a Galvanically Isolated DC-DC Converter

This paper presents layout techniques and optimizations applicable to high-voltage, chip-integrated, galvanically isolated transformers implemented on a thick oxide standard CMOS process. A novel shield implementation for reduced inter-coil capacitance and improved CMTI performance is discussed. Benefits and impacts of the shield in terms of CMTI-coupled currents, quality factor and transformer power-transfer efficiency are modeled, simulated and presented. An accurate distributed circuit simulation model, derived from the y-parameters produced by a 3D finite-element planar electromagnetic solver is assessed. The circuit simulation model supports the design of the CMOS-integrated power conversion system embedding the transformer.