Efficient design of application specific DSP cores using FPGAs

This paper focuses on design of digital signal processing (DSP) cores for compact and efficient implementations of real time DSP applications on field programmable gate arrays (FPGAs) using distributed arithmetic. The resulting serial distributed arithmetic (SDA) and the parallel-distributed arithmetic (PDA) designs are implemented. As an example, the implementation of a 16-tap 8-bit Finite impulse response (FIR) filter on a Xilinx XC4000E FPGA using SDA and PDA techniques has been examined. An analysis of the performance comparison is described. The results show that PDA designs with a digit size of 2 bits are more efficient in area-time product parameter than those of SDA implementations.