Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]

In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus making the decoder suitable for HDTV.