Clock and data recovery circuit for 2.5Gbps Gigabit Ethernet transceiver

This paper describes a clock and data recovery circuit that operates at 2.5Gb/s in a 1.8V 0.18um digital CMOS technology. It is a main part of the receive path in a fully integrated CMOS SerDes transceiver. A frequency-aided PLL-based dual-loop architecture is adopted. To suppress the noise, a ring oscillator composed of differential buffer delay stage is introduced that employs some technique to lower the gain. A special data-triggered phase/frequency detector is also described. A transistor-level simulation shows the overall lock behavior.