System Level Power Supply Induced Jitter Suppression for multi-lane high speed serial links

This paper presents a system-level co-optimization approach with Chip Power Model based power integrity simulation of the power delivery network and jitter sensitivity transfer function (JTF). Due to the need to merge multiple power domains and to locate adjacent power domains close to each other for enhancing cost effectiveness and space efficiency, the coupling resonance severely affects the whole system. To meet the rigorous performance requirements, a system-level co-design is mandatory. An approach which analyzes the V-by-One IP circuit blocks and finds the critical path based on the JTF is suggested within the case studies. An on-chip level optimization to bring higher voltage controlled oscillator output frequency and to add sufficient On-die-cap was analyzed. In the off-chip design stage, various design modifications to split the power domain, reinforce the ground path, and add package decoupling capacitors were attempted to decrease total jitter by the JTF. Finally, a co-optimization design process workflow which controls the total jitter budgeting is presented. The total jitter is decreased by 68.49% compared to the worst design case.