Die Floorplan and PKG Design Impacts on Power Integrity Performances of Multiple Blocks in a Single Power Domain

High cost of high-end silicon manufacturing processes are squeezing die sizes and pushing multiple blocks in a single power domain to be placed in narrow and long area. Consequently, these blocks have poor power integrity environment due to narrow and long shape PKG PDNs following their narrow and long shaped die floorplan. The several power integrity performances are studied according to floorplans, PKG PDN designs, and current scenarios of the multiple blocks. The narrower and longer shaped floorplan leads higher PKG PDN impedance due to lower sharing ability of on-die decoupling capacitors, and resulting larger power domain voltage drop. These voltage drops become larger as di/dt level of each scenario is bigger and frequently happens.