Advanced Chip Last Process Integration for Fan Out WLP

Wafer-level packaging (WLP) is an advanced packaging technique to integrate heterogeneous chips together in microelectronics. Herein we propose a low cost and small form factor package structure processed by Chip Last Fan Out WLP. This paper introduces a single package interposer with fine pitch lines and Cu post for FOWLP which enables to overcome package size limitations. The proposed organic interposers for Fan Out WLP are expected to be a promising solution for high performance wafer-level system-in-package (SiP) architectures. For high-end applications, this study demonstrates high functionality package that interconnects multiple chips into one single system. The process of combining and scaling of the package into one small form factor presents many challenges such as controlling the warpage and applying the proper design layout of the RDL to reroute the I/O for distinguished functions. In this study the design rule of the package, optimization of fabrication process has been successfully demonstrated. Reliability tests has been performed to confirm the thermo-mechanical stress applied to the package.