Wafer Stacked Wide I/O DRAM with One-step TSV Technology

A cost-effective TSV technology called "one-step TSV" is applied to wafer stacked wide I/O DRAM. After planarization of incoming wafers, face-to-face (F2F) fusion bonding is done for DRAM wafers followed by TSV fabrication to electrically connect each DRAM layer. The memory bus width is 32 bits per layer, and the total memory bus width becomes 32 bits multiplied by the number of layers. Leakage current, TSV resistance, storage capacitance of DRAM cells and threshold voltage Vth of nMOS and pMOS are evaluated, and no degradation due to wafer stacking and TSV process is confirmed. Process feasibility of one-step TSV is successfully demonstrated for 2-layer wide I/O DRAM.