On-Chip Transient Hot Spot Detection with a Multiscale ROM in 3DIC Designs

Limitations in traditional methods of thermal analysis call for novel methods to meet emerging needs for chip thermal simulation. The goal in this work is to describe a method to perform transient thermal simulations on chips in multi-chip systems and 3DIC packages, while accomplishing the following key objectives: (1) Capture on-chip hot spots with fine-grain resolution (2) Account for system-level thermal effects (3) Rely on minimal chip-package-system (CPS) thermal characterization (4) Provide extremely fast solutions (e.g. in seconds), and (5) Provide excellent accuracy compared to full fidelity models based on, for example, computational fluid dynamics (CFD), e.g. within 5% error. The method described is an innovative multiscale, distributable, system modeling approach with black box Reduced Order Model (ROM) that overcomes challenges with traditional CPS thermal modeling to meet the stated goals. The method is composed of the following components: (1) Efficient thermal characterization of chip-, package-, and system (2) Black box ROM generation (3) Multiscale ROM assembly (4) Multiscale power accounting, and (5) Distributed solution for thermal evaluation of points on chip. The described methodology is validated for several test cases including 3DIC, the results of which are presented. Accuracy and significant speedup factor greater than 10
⁴
was observed in the test cases, and actual speedup is expected to be much greater than this. The description of the novel method and presentation of validation results, including those for 3DIC, demonstrate its ability to overcome the limitations in traditional methods of thermal analysis to meet emerging needs for chip thermal simulation.