Low cost copper based sintered interconnect material for optoelectronics packaging

A low cost copper sintered interconnect for packaging of high power automotive LEDs is presented. The reliability of sintered interconnects is investigated by automated transient thermal analysis (TTA), scanning acoustic microscopy (SAM). Finally, cross-sectioning is performed to show the effectiveness of the non-destructive test methods. TTA and SAM analysis are observed to corroborate well together and provide a definitive analysis of the performance of the sintered interconnect both as sintered and also after temperature shock tests.The unique property of the Cu flakes to stack over each other leads to a thin bond line of < 20 μm and thin and long pores. In well sintered interconnects, this leads to a closed packing structure with porosity < 10% even when sintering under a low bonding pressure of 10 MPa.Encapsulated samples are observed to show slower degradation under high thermo-mechanical stress conditions, compared to non-encapsulated samples. In well sintered samples with comparable porosity, encapsulated as well as non-encapsulated samples showed similar degree of degradation of < 10% after 250 temperature shock cycles. However, in samples which showed a relatively poor thermal performance under initial conditions, the degradation in the non-encapsulated samples was up to 4 times higher than the encapsulated samples.The sintering process can induce stress in the chip, which can be detrimental to reliability of the package. Therefore, μ-Raman spectroscopy is conducted to understand the stress developed in the silicon chip after sintering and compare it to traditional Au80Sn20 solder. Compared to a well soldered Au80Sn20 sample, the Cu sintering interconnect showed reduced biaxial stress of almost 30% even when the sintered bondline thickness is 40% lesser than that of Au80Sn20.