Solutions to Overcome Warpage and Voiding Challenges in Fanout Wafer-level Packaging

Recent developments in microelectronics packaging have been driven by high performance and miniaturization needs. Wafer-level fanout packaging along with other advanced 2.5D/3D architectures has gained momentum to enable tighter pitch scaling and increased interconnect densities. One primary challenge with the wafer-level assembly is wafer warpage due to high CTE-mismatch between the Si and wafer-level underfill. While there have been studies to address wafer warpage, the consolidated impact of these solutions to voiding and reliability has not been well understood. This paper explores different material and process parameters that can modulate warpage and voiding for wafer-level packaging. Stacked die to wafer test vehicle was used for data collection. C-mode Scanning Acoustic Microscopy (CSAM) was used to characterize voiding performance. Different materials were evaluated along with their interaction with process and equipment to provide a comprehensive working window to achieve a void-free process along with relatively low wafer warpage.