Tracking in-die mechanical stress through silicon embedded sensors for advanced packaging applications

Advanced IC’s built with recent technology nodes take advantage of the process induced mechanical stress, which is used as one of the transistor performance boosters. Modulation of the stress level, experienced by silicon chip, has significant impact on its performance and reliability. Therefore, monitoring of this stress through wafer manufacturing and packaging process is of high importance. We have developed an in-die-embedded stress sensor, testable with standard product test that can with help measuring and monitoring stress level in the die. The sensor design was demonstrated for multiple advanced FinFET technology nodes (< 14nm). We have confirmed high sensitivity across process corners and temperature with consistent results between electrical wafer sort (EWS) and final test (FT). The results from the mechanical stress sensors indicate that the stress non-uniformity across the wafer is preserved through wafer dicing/thinning/packaging process. Statistical analysis of the sensor results enables detection of wafer patterns and outlier identification at EWS and subsequent FT after assembly enables detection of abnormal mechanical stress changes due to packaging. This mechanical stress sensor provides differentiated data for EWS, FT, and Burn-In (BI) to create product relevant screening specs for improved product reliability and can provide an early alarm for the product reliability risk due to effects such as delamination or cracks. This sensor has been implemented in the PDF Solutions’ CV Core
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system which enables for in-field tracking and analyzing the sensor signals to detect and mitigate the potentially disastrous reliability failures.