System-level verification of a packaged silicon photonics-based transceiver

In this paper, we demonstrate how a realistic sub-system-level verification could be performed on a packaged optical transceiver, including on-chip silicon photonic components, its package, and electrical chips’ performance altogether.Silicon photonics has been considered as a promising candidate for ultra-compact, high speed, and cost-effective photonics integration platforms. One commercial silicon photonics chip typically includes dozens of optical components, from waveguides to functional passive and active devices. Such photonic chips are then packaged with electronic driver and control integrated circuits, forming a relatively complex sub-system. Existing silicon photonics design processes typically begin with the design and optimization of every single photonic component, and subsequently simulate the impact of packaging by building an equivalent circuit for the photonic components and electronics using commercial electrical EDA software. However, such an approach does not evaluate the sub-system level opto-electrical performance and thus is not sufficient for design verification before tape out.In this paper, using a packaged silicon photonic coherent transceiver as an example, we demonstrate how sub-system-level verification could be performed considering on-chip photonic components, electronics, and package all at the same time. The photonic components evaluated include both foundry PDK cells and self-designed devices. Transmission characteristics of electronic chips and impacts of packaging are included in the simulations. As most of the commercial EDA software tools available are specialized in either the optical or electrical field, our evaluation process involves using multiple software tools to thoroughly verify the chip design and sub-system performance. We perform the simulations for the photonic devices and electronic chips on the corresponding software tools and use the results as input for next-level simulation. Lumerical FDTD is used for photonic component verification, Keysight Advanced Design System is used to add the package impacts and the transmission characteristics of the electronic devices, and Lumerical Interconnect is used for chip and sub-system level verifications. Last, we will discuss the issues we encountered during the device to sub-system level evaluation and how we addressed or proposed to address them. We believe that by combining the available software tools, the evaluation process described above would be a very useful way to verify the chip and package design before tape-out, enabling fast and reliable chip designs.