A Hybrid Panel Level Package (Hybrid PLP) Technology Based on a 650-mm x 650-mm Platform

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package dimensions, applications such as an application processor (AP) or multichip module (MCM) will have greater benefits than the smaller power management integrated circuit (PMIC), transceiver or audio codec applications typical of chip-first FO packaging.The known technical challenges with panel-level fan-out (PLFO) packaging range from die-shift over the full panel, through warpage of the panel along the process flow which limits the number of redistribution layers, to controlling the total thickness variation (TTV) during the panel-level back-grind processes. Commercial aspects such as capital expenditures on panel-level equipment and difficulty in filling a panel line are the main financial considerations.A 650-mm x 650-mm PLFO technology will be presented which enables assembly of four 300-mm round or 300-mm square fan-out subpanels on a carrier panel. This technology enables the reutilization of the reconstitution and die / package-level processing equipment, focusing the panel processing where the greatest cost benefit can be achieved in the redistribution layer process. The use of a carrier panel minimizes the warpage permitting implementation of more RDLs without impacting processability. The reconstitution portion of the flow is performed on the smaller form factor minimizing die-shift considerations on the large panel. The same panel equipment and infrastructure can also be used for chip-last PLFO or high-density, high-quality coreless substrates. Process flow details will be shared based on a PLFO pilot line.Component level reliability results on a chip-last fan-out test vehicle will be shown as well as comparative cost modelling on chip-first PLFO vs 300-mm fan-out wafer for both chip-first and chip-last fan-out packages.