Numerical Evaluation on SiO2 Based Chip to Wafer Hybrid Bonding Performance by Finite Element Analysis

This paper presents a numerical study on the SiO
2
/Cu Chip-to-Wafer Hybrid Bonding (C2W-HB) process. The annealing process is modelled using the Finite Element Analysis tool. The effects of Cu dishing and Cu pad thickness, annealing temperature and dwell duration are investigated. The result discussions are focused on the bonding performance regarding the Cu bonding area and peeling stress on the dielectric bonding interface. Larger Cu bonding area and lower dielectric peeling stresses are desired to achieve a good bonding performance while avoiding dielectric delamination or crack. This numerical study provides some insights on the process and the results could be useful to establish the process guidelines.