Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS

Runtime monitoring is a lightweight verification technique that ensures correct execution of a system based on a specification, e. g., in Linear Temporal Logic (LTL). c-LTL is an extended semantics of LTL that speculates on the property’s future satisfaction, by this, warning before potentially violating a correctness specification.Our framework generates high-level synthesizable C++ code implementing runtime monitors for c-LTL properties. We evaluate the resource utilization and performance of the monitors obtained from the framework. Synthesis techniques and our dedicated optimizations cut down the required number of LUTs by up to 93%, allowing an effective implementation of runtime monitors.