Impact of Process Variations on the Performance of a Widely Tunable CMOS Transconductor

The methodology followed to determine the impact of process variations on the experimental behavior of a widely tunable transconductor, is presented. The principle of operation of the linearized transconductor is based on subtracting the responses of two matched voltage-to-current converters. As a result, the simulated transconductance of the cell can be continuously tuned over around three decades, from 27.96 μA/V to 33.6 nA/V. The circuit has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8 V supply. The experimental characterization of 8 samples of a silicon prototype reported a measured range of the transconductance between 20.57 μA/V and 1.42 μA/V. Montecarlo and corner simulations have been carried out to ascertain the origin of this noticeable deviation.